1. Field of the Invention
The present invention relates generally to computer graphics systems and, more particularly, to a method of providing efficient screen to screen block image transfer operations in a graphics subsystem having a sliced frame buffer architecture.
2. Description of the Related Art
In the computer graphics field, many types of graphics subsystems are utilized. Typically, however, such subsystems provide for a frame buffer to store pixel data to be eventually displayed on a screen. The frame buffer is made up of a displayable and a non-displayable memory portion. The displayable memory portion of the frame buffer is usually an exact mapping of the display screen. That is, each storage location in the displayable portion corresponds to a display location or pixel on the screen.
When moving pixels from one area of the screen to another, block image transfer (BLIT) is most often utilized. BLIT operations include moving blocks or lines of pixels from one location of the displayable portion of the frame buffer to another. The implementation of a screen to screen BLIT operation is well-known in the art and thus, is not explained.
In application Ser. No. 08/572,697, filed on Dec. 14, 1995, which has issued as U.S. pat. No. 5,724,560, assigned to Internal Business Machines Corporation, the disclosure of which is hereby incorporated by reference, a novel method of rendering pixel data from a graphics subsystem's processor(s) to a frame buffer was disclosed. The method entailed decomposing (or slicing) each pixel data into its RGB color components before transferring the data to the frame buffer. The frame buffer itself was divided or sliced into three memory banks, each bank being used to store one of the three color components of each pixel. Each color component of the pixels was assembled and rendered together. For example, using a 32-bit bus to render 24-bit pixel data to the frame buffer, each pixel data would first be decomposed into eight bits of red, eight bits of green and eight bits of blue data. All the bits representing the red components of the pixels were assembled and transferred to the red memory bank of the frame buffer. So were the bits representing the green and the blue components assembled and transferred to the green and blue memory banks, respectively. This rendering method allowed all 32 bits of the bus width to be effectively used at each bus cycle since the transferred data was packed in blocks of eight bits. In contradistinction, rendering a whole pixel at a time only allowed 24 bits (or 3/4) of the bus width to be used at each bus cycle. Hence, a marked increase in speed was achieved. Furthermore, in this configuration only one bus was used to link the three memory banks to the subsystem's processor(s). Therefore, a savings in chip's cost and real estate was realized while augmenting the efficiency of the subsystem.
However, when a screen to screen BLIT operation was performed in the sliced frame buffer architecture, each pixel was moved one component at a time. This involved reading a particular component of the pixel's RGB data from one location of a memory bank and writing it into another location, disconnect the data bus from the memory bank from which the component was read and connect the data bus to another memory bank to allow the next RGB component of the pixel to be moved. Thus, moving a block or a line of pixels from one area of a screen to another required that a bus cycle be spent disconnecting/connecting the data bus to a different memory bank after each component of a pixel was moved. Hence, the number of disconnecting/reconnecting cycles depended on both the number of memory banks in a frame buffer and the number of pixels being moved. Consequently, a screen to screen BLIT often times was quite a time intensive operation.
Thus, there is a need in the art for an apparatus and method of decreasing the time required to perform a BLIT operation in a sliced frame buffer architecture.